Circuit with a sensor and non-volatile memory having a ferroelectric dielectric capacitor

ABSTRACT

A circuit includes a sensor delivering a charge, a capacitor non-volatilely storing the charge, and a read and reset circuit reading out the stored charge. The capacitor has further connection terminals connected to the read and reset circuit and in parallel with the sensor terminals, and a ferroelectric storage dielectric intermittently connected to the sensor. The sensor can be a photodiode, a phototransistor, a Hall sensor, or a thermoelement. A switch can be connected between one of the further terminals and one of the sensor terminals. Preferably, the switch is a transistor and a drive circuit drives it. The sensor and the capacitor are formed in a semiconductor body. During a storage procedure, time periods during which the switch is on are coordinated with the sensor and/or capacitor to keep an electrical field present between the further terminals below a maximum value at which the ferroelectric dielectric saturates.

BACKGROUND OF THE INVENTION FIELD OF THE INVENTION

The present invention relates to a circuit arrangement having a sensorand a storage means for the nonvolatile storage of a charge delivered bythe sensor.

Sensors are used for recording nonelectric variables and for conversionto variables which can be measured electrically, such as current,voltage or electrical charge. Nonvolatile storage of the chargedelivered by the sensor has hitherto been associated with considerablecomplexity. As an example, CCD cameras should be mentioned in thisregard, said cameras having a multiplicity of light-sensitive sensorswhich are arranged in a similar manner to a matrix and at which anelectrical charge is generated when light is incident, The chargesgenerated at the individual sensors are read out and converted in anamplifier unit to voltages which can be used for programming nonvolatilememory cells, such as flash EEPROMs. Besides the high level of circuitcomplexity, the provision of a high supply voltage suitable forprogramming the EEPROMs and the relatively large space requirement,which arises as a result of the provision of an amplifier circuit andthe physically separate arrangement of the sensor matrix and the storagemeans, a particular disadvantage of such apparatuses is that theaforementioned nonvolatile memories only permit digital values to bestored.

If, by way of example, in the case of light sensors, the amount ofcharge generated by the sensors is dependent on brightness, part of thebrightness information is inevitably lost when this charge is storedusing the aforementioned storage means. If each sensor has only oneassociated memory cell, the stored value can be used only to distinguishwhether the brightness at the sensor was above or below a prescribedthreshold value More exact storage of the analog value delivered by thesensor requires analog/digital conversion of this analog value andstorage of the digital value obtained in this process, the number ofmemory cells required for storing the digital value depending on thenumber of places in the digital value.

U.S. Pat. Nos. 5,325,050 and 5,332,962 describe circuit arrangementshaving a sensor and a storage means for the nonvolatile storage of acharge delivered by the sensor, the storage means being a capacitorhaving a ferroelectric storage dielectric which is at leastintermittently connected to the sensor element.

SUMMARY OF THE INVENTION

The circuit arrangements described also have a DC voltage source whichis intermittently connected to the ferroelectric capacitor in order toproduce spontaneous polarization of the dielectric, and a polarizationdetector to establish whether the polarization of the ferroelectriccapacitor has changed on account of a voltage signal delivered by thesensor.

In this way, as in the aforementioned circuit arrangements described, itis only possible to establish whether a prescribed maximum value for thesensor signal has been exceeded This case therefore also presents onlyanalog/digital conversion of an analog sensor signal.

The document EP 0 402 248 A2 relates to a photosensor having an analogstore connected. The way in which such a circuit arrangement can beproduced easily and the means used to do so are not disclosed.

The present invention was therefore based on the object of providing acircuit arrangement having a sensor and a storage means which easilypermits the storage and evaluation of analog values delivered by thesensor, which can be produced as an integrated circuit arrangement, inparticular, and for which the aforementioned disadvantages do not arise.

This aim is achieved by the circuit arrangement mentioned in theintroduction, in which the storage means is a capacitor having aferroelectric storage dielectric which is at least intermittentlyconnected in parallel with connection terminals of the sensor.

The capacitor having the ferroelectric storage dielectric permitsnonvolatile storage of the charge delivered by the sensor. The capacitoris connected to the sensor, possibly via a switch. This means that it ispossible to integrate the sensor and the capacitor in the samesemiconductor body, the result of which is a very small spacerequirement for producing the circuit arrangement according to thearrangement. The matrix-like arrangement of an appropriately largenumber of light-sensitive sensors, such as photodiodes, which each havean associated capacitor with a ferroelectric storage dielectric, thuspermits all the components necessary for detecting and storing images tobe accommodated on one chip.

The present invention is not restricted to the use of light-sensitivesensors, however. Instead, it can be used anywhere where the use ofsensors and storage of the values delivered by the sensors are requiredand where the smallest possible physical form is desirable, such as inmicromechanics.

Advantageous refinements of the invention are the subject-matter of thedependent claims.

To store the charge delivered by the sensor, the sensor can bepermanently connected in parallel with the connection terminals of thesensor by means of a fixed line connection. By way of example, when thecircuit arrangement according to the invention is used for imagedetection, this is a preferred embodiment if an aperture is provided infront of the light sensors which permits the light sensors to be onlyintermittently exposed to light. If the light sensors are in the form ofphotodiodes, an approximately constant voltage drops between theconnection terminals thereof upon exposure to light, the currentdelivered by the sensors or the charge delivered to the capacitors perunit time depending on the light intensity at the respective lightsensor. The charges delivered by the individual sensors and stored atleast in part in the capacitors thus represent a measure of the meanilluminance at the sensor while the aperture is open. The capacitorsthus store an item of image information, the resolution of the imageresulting from the number of light sensors arranged in matrix form.

In one embodiment of the invention, a switch, in particular in the formof a transistor, is connected between a terminal of the capacitor and aconnection terminal of the sensor element. In this case, the switchfulfills the function of the aforementioned aperture. Turning on theswitch determines the instant at which the charge generated by thesensor or sensors is to be stored in the capacitor or capacitors.

Preferably, for reading out the charge stored in the capacitor, a readand reset circuit connected to at least one terminal of the capacitor isprovided.

The design and manner of operation of the circuit arrangement accordingto the invention are explained in more detail below with the aid ofillustrative embodiments in the figures of the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a circuit diagram of an embodiment of the circuitarrangement according to the invention;

FIG. 2 shows a curve for the electrical field E_(i) in the ferroelectricstorage dielectric as a function of the electrical field E_(e) appliedto the capacitor externally;

FIG. 3 shows a circuit arrangement according to the invention havingexternal wiring when a number of sensors and capacitors in a matrix-likesensor and storage arrangement are used;

FIG. 4 shows a cross section through an inventive circuit arrangementintegrated in a semiconductor body.

Unless otherwise stated, the same reference symbols denote the samecomponents with the same meaning in the figures.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 shows a circuit diagram of the inventive circuit arrangementhaving a sensor S and a capacitor C_(F) which has a ferroelectricstorage dielectric. The capacitor C_(F) and the sensor S, which is inthe form of a photodiode in the example illustrated, are each connectedto a common reference-ground potential M by means of a connectionterminal AK2, AK4. Another connection terminal AK3 of the capacitorC_(F) is connected to another connection terminal AK1 of the sensor Svia the load path of a field effect transistor T1 acting as a switch. Todrive the transistor T1, there is a first drive circuit AS1, which isconnected to the gate connection G of the transistor T1 and, by drivingthe transistor T1, determines the instant and the length of time forwhich there is a conductive connection between the capacitor C_(F) andthe sensor S.

The manner of operation of the circuit arrangement will be describedbelow for the use of a photodiode as sensor S.

When light is incident on the photodiode S, an approximately constantvoltage drops between the connection terminals AK1, AK2 thereof, thecurrent delivered by the photodiode S being dependent on the intensityof the incident light.

The use of a ferroelectric dielectric in the capacitor C_(F) permits atleast some of the charge flowing from the photodiode S to the capacitorC_(F) when the transistor T1 is on to be permanently stored. Thephenomenon of this permanent charge storage is explained with the aid ofthe hysteresis curve shown in FIG. 2, which shows the profile for anelectrical field E_(i) forming inside the ferroelectric dielectric as afunction of an external electrical field E_(e) applied to capacitorplates—between which the dielectric is situated. This externalelectrical field E_(e) is dependent on the voltage U_(c) present betweenconnection terminals of the capacitor C_(F).

When an external electrical field E_(e) is present, an internal fieldE_(i) is formed in the ferroelectric dielectric, the values of saidinternal field being situated on curve sections K1, K2 with differentprofiles, depending on whether the external electrical field E_(e)increases toward positive values starting from a negative value−E_(emax) or whether the external electrical field E_(e) decreasestoward negative values starting from a positive value E_(emax). After apoint on the hysteresis curve, denoted as lower saturation point D, thecurve sections K1 and K2 run together when the amount of the negativeexternal electrical field exceeds the value E_(emax). Likewise, thecurve sections K1, K2 run together after an upper saturation point Bwhen the amount of the positive external electrical field E_(e) exceedsthe value E_(emax).

If applying a negative external electrical field E_(e) sweeps throughthe hysteresis curve as far as the lower saturation point D and turnsoff the external electrical field E_(e) or a voltage present on thecapacitor terminals AK3, AK4, a negative internal electrical field withthe value −E_(iR) is maintained in the storage dielectric, as becomesclear from FIG. 2 at point A on the hysteresis curve. If the hysteresiscurve is swept through as far as the upper saturation point B as aresult of a positive external electrical field being applied, a positiveinternal electrical field with the value E_(iR) remains in the storagedielectric after the external field has been turned off, as becomesclear at point C on the hysteresis curve.

The internal electrical field E_(i) which remains after the externalelectrical field E_(e) has been removed results from permanentpolarization of the ferroelectric dielectric, the extent of thepolarization and hence the strength of the internal electrical fielddepending on the value of the external electrical field E_(e) appliedbeforehand. If, for example as a result of a smaller positive externalelectrical field E_(e) being applied, the hysteresis curve is sweptthrough only as far as point B′, weaker polarization of the dielectrictakes place, so that a smaller internal electrical field with the valueE_(iO) remains after removal of the external electrical field E_(e).Increasing the magnitude of the negative or positive external electricalfield E_(e) beyond E_(emax) or beyond the saturation points D and Bcauses no increase in the magnitude of the internal electrical fieldE_(i) which remains after the external electrical field E_(e) has beenturned off.

The internal electrical field E_(i) which remains after removal of theexternal electrical field E_(e) as a result of polarization of thedielectric has permanent charge storage on the capacitor plates of thecapacitor C_(F) associated with it, the value of the stored chargedepending on the value of the internal electrical field and hence on theexternal electrical field E_(e) applied in order to store the charge oron the voltage U_(c) present between the capacitor terminals AK3, AK4.

The cycle of a storage procedure will be explained below, the sensor Sbeing assumed, by way of example, to be a photodiode which, when lightis incident, generates an approximately constant positive voltagebetween its connection terminals AK1, AK2 and hence, when connected inparallel with the capacitor C_(F), produces a positive externalelectrical field between the capacitor plates. The photodiode delivers acurrent which is dependent on the illuminance; the brightnessinformation is thus mapped onto the current delivered by the sensor.

Before a charge delivered by the sensor S is stored, the capacitor C_(F)is “reset”. This is done by applying a negative voltage, as a result ofwhich the hysteresis curve shown in FIG. 2 is swept through as far asthe lower saturation point D. The negative voltage can be applied, asshown in FIG. 1, by connecting the connection terminal AK3 of thecapacitor C_(F) to a terminal for a potential V− which is negative withrespect to the reference-ground potential M. As explained above, anegative internal electrical field with the value −E_(iR) remains in thestorage dielectric after the negative voltage has been turned off.

If the capacitor C_(F) is subsequently connected in parallel with thesensor S as a result of the transistor T1 turning on, when light isincident on the sensor S a charge generated by the sensor S flows to thecapacitor plates of the capacitor C_(F). This charge causes an externalelectrical field E_(e), which in turn causes the value of the internalelectrical field E_(i) to rise from the value −E_(iR) at point A on thehysteresis curve in accordance with the curve profile for the curvesection K2 toward the upper saturation point B. After the transistor T1has turned off, no further charge flows to the capacitor C_(F). Thevoltage U_(c) established between the capacitor terminals by the flow ofcharge, or the external electrical field E_(e), is maintained at firstafter the switch T1 has turned off. However, unavoidable leakagecurrents cause some of the charge stored on the capacitor plates to flowaway until the external electrical field E_(e) becomes zero. Remainingpermanently stored on the capacitor plates is that part of the chargewhich results from the internal electrical field E_(i) remaining afterremoval of the external electrical field E_(e). If no light is incidenton the photodiode S and hence no charge flows to the capacitor C_(F),the internal electrical field remains at the value −E_(iR).

The capacitor is suitable both as an analog storage medium and as adigital storage medium. To use it as an analog storage medium, it isnecessary to ensure that the external electrical field E_(e) assumesvalues between 0 and less than E_(emax) after the capacitor has beenreset, and the internal electrical field E_(i) then assumes valuesbetween −E_(iR) and E_(iR) after removal of the external electricalfield. The charge permanently stored on the capacitor plates isproportional to the remaining internal electrical field E_(i) and henceis dependent on the external electrical field E_(e) which is present onthe capacitor for storage, The value of the external electrical field isdependent on the charge flowing to the capacitor plates when thetransistor T1 is on, the external electrical field E_(e) and the chargeQ which flows to the capacitor plates having the following relationship:

E_(e)=Q/(A·∈),

where A denotes the capacitor surface area and ∈ denotes the dielectricconstant of the storage dielectric.

On the other hand, the charge flowing to the capacitor plates depends onthe voltage produced between the connection terminals AK1, AK2 of thesensor S and on the length of time for which the turned-on transistorpermits a flow of charge. The parameters capacitor surface area A,voltage drop U_(s) on the sensor and turned-on time of the transistor T1are coordinated with one another, for the purpose of storing analogvalues, such that the value of the positive external electrical fieldalways assumes values less than or equal to E_(emax). Thus, by way ofexample, increasing the size of the capacitor surface area can slow downthe rise in the external electrical field E_(e) when the flow of currentis constant, and hence can increase the sensitivity of the arrangement.In addition, the capacitor surface areas need to be chosen such that thecapacitor C_(F) does not saturate immediately when charge is deliveredby the sensor S when the transistor T1 is on.

In accordance with a first embodiment, the sensor S and the capacitorC_(F) are coordinated with one another such that the voltage produced onthe sensor U_(s) is sufficient to bring the capacitor to the uppersaturation point, that is to say the sensor S produces an external fieldE_(e) whose value is greater than or equal to E_(emax) when thetransistor T1 is on for long enough. When a photodiode is used, thebrightness information is mapped onto the current delivered by thephotodiode. Since the capacitor C_(F) can only hold a particular amountof charge before it saturates, the transistor T1 only permits a flow ofcurrent for a prescribed length of time, which means that the chargestored in the capacitor C_(F) can be used to draw conclusions about thecurrent flowing for storage and hence about the brightness informationon the sensor. The length of time for which the transistor T1 is on isequivalent to the aperture time in photographic equipment. Thus, thearrangement according to the invention also permits the aperture time tobe reduced for high illuminance, in order to prevent saturation of thecapacitor C_(F) as a result of the large charging current delivered bythe sensor S for a high level of brightness.

In a further embodiment, a sensor is used which delivers differentvoltage values between its output terminals AK1, AK2, depending on thebrightness. The brightness values on the sensor are thus mapped ontodifferent voltage values on the sensor. These different voltage valuesproduce different values for the external electrical field E_(e) on thecapacitor C_(F), the sensor being chosen such that the voltages betweenits connection terminals produce no values for the external electricalfield greater than E_(emax) in order to store analog values. In thisembodiment, the length of time for which the transistor is on may bevery long, or the transistor T1 may be dispensed with.

To use the capacitor as a digital storage medium, the sensor S and thecapacitor surface area A of the capacitor C_(F) are coordinated with oneanother such that the capacitor C_(F) always saturates when it isconnected in parallel with the sensor S and the sensor delivers acharging current as a result of exposure to light. The sensor S ispreferably in the form of a photodiode for this embodiment, the voltageU_(s) produced between its connection terminals AK1, AK2 when light isincident being sufficient to saturate the capacitor. So that thecapacitor is always saturated when a charging current flows, a verysmall capacitor surface area A and long turned-on times for thetransistor T1 are chosen, for example.

For reading out the charge stored in the capacitor C_(F) by means of thesensor S, a read and reset circuit LRS is provided. The read and resetcircuit LRS has a sense amplifier LV which is connected to the firstconnection terminal AK3 of the capacitor C_(F) via the load paths ofthird and fourth transistors T2, T4. The transistors T2, T4 are drivenby means of a second drive circuit AS2, which turns on the transistorsT2, T4 for the purpose of reading out the charge stored in the capacitorC_(F).

Once the reading procedure has ended, the capacitor C_(F) is reset, thefirst connection terminal AK3 of the capacitor C_(F) being connected tothe terminal for negative potential V− via the load path of thetransistor T2 and the load path of a further transistor T3, which canlikewise be driven by the second drive circuit AS2. Once the read andreset procedure has ended, the transistor T2 is turned off under thecontrol of the drive circuit AS2.

FIG. 3 shows the inventive circuit arrangement having the sensor S, thecapacitor C_(F) and the transistor T1, connected between connectionterminals AK1, AK3 of the sensor S and of the capacitor C_(F), as partof a matrix-like arrangement of such a sensor and storage arrangement,which each have a sensor S and a capacitor C_(F). Each sensor andstorage unit is connected to one bit line BL and to in each case twoword lines WL1, WL2, each sensor and storage unit being unambiguouslyidentifiable using the bit lines BL and word lines WL1, WL2 to which itis connected. Thus, no two sensor and storage arrangements are connectedto the same bit lines and word lines BL, WL1, WL2. A first word line WL1is used to drive the transistor T1 arranged between the sensor S and thecapacitor C_(F), the first word line WL1 being able to be connected bymeans of a transistor T6 to a drive potential V+ which is sufficient toturn on the first transistors T1. The transistor T6 is driven by meansof a drive circuit (not shown in more detail here), the operation ofthis drive circuit being equivalent to that of the first drive circuitAS1 (shown in FIG. 1), since the first transistors are on for as long asthe transistor T6 is on and the first word line WL1 is thus at drivepotential V+ When the transistor T6 is driven, all the first transistorsT1 connected to the first word line WL1 are turned on in order to storea charge generated by the sensors S on the capacitors C_(F).

In addition, a second word line WL2 is provided which is connected tocontrol connections of the second transistors T2 in the sensor andstorage arrangements. The second word line WL2 can be connected to aterminal for drive potential V+ via a transistor T5, the secondtransistors T2 being on when the transistor T5 is on and the word lineWL2 is at drive potential V+. The transistor T5 is driven by means of adrive circuit (not shown in more detail here). The bit line BL has athird and a fourth transistor T3, T4, whose operation is equivalent tothat of the transistors T3, T4 shown in FIG. 1. These transistors T3, T4are driven by means of a drive circuit (not shown in more detail here),the fourth transistor T4 being on when the second transistor T2 is alsoon and the charge stored in the capacitor C_(F) is to be read out bymeans of the sense amplifier LV. The third transistor T3 is on when thesecond transistor T2 is also on, in order to reset the capacitor C_(F)as a result of connection to the negative potential V−.

In the illustrative embodiment shown, the sense amplifier LV is usedboth for reading out the charge stored in the capacitors C_(F) and foramplifying and forwarding the ascertained value to further processingunits.

FIG. 4 shows a cross section through a semiconductor body containing asensor and storage arrangement having a sensor S, a first transistor T1,a capacitor C_(F) and a second transistor T2. In this embodiment, ap-doped well is doped into a silicon substrate SI. The transistors T1,T2 are in the form of n-channel CMOS transistors, the drain/sourceregions of the transistors T1, T2 being in the form of n+-doped regionsin the p-doped well. In FIG. 4, the reference symbols G1, G2 denote thegate electrodes, the reference symbols S1, S2 denote the source regionsand the reference symbols D1, D2 denote the drain regions of thetransistors T1, T2. The first and second transistors T1, T2 have acommon drain/source region D2, S1 which is connected to a firstcapacitor plate KP1 of the capacitor C_(F) above the silicon substrateSI.

Arranged between the first capacitor plate KP1 and a second capacitorplate KP2 above the latter is a ferroelectric dielectric D1. The sourceregion S2 of the second transistor T2 is connected to a bit line BL viaa contact K so as to be electrically conductive. The gate electrodes G1,G2 of the first and second transistors T1, T2 simultaneously form thefirst and second word lines WL1, WL2, the bit line BL and the word linesWL1, WL2 running approximately at right angles to one another in thearrangement shown.

The sensor in the form of a light-sensitive diode in this illustrativeembodiment is formed by the pn junction between the n+-doped region D1,which simultaneously represents the drain region D1 of the firsttransistor T1, and the p-doped well. In order to permit light to beincident on the n+-doped region D1, the bit line BL is moved past thesensors S and the insulation layer OX applied above the siliconsubstrate SI is designed to be translucent or permeable to radiation.Advantageously, the insulation layer OX is thinned above the n+-dopedregion D1 in order-to permit improved incidence of light.

The second capacitor plates KP2 of all the sensor and storagearrangements are preferably in the form of continuous electrode plateswhich are connected to a reference-ground potential.

We claim:
 1. A circuit, comprising: a sensor for delivering a charge,said sensor having connection terminals; a capacitor for non-volatilestorage of said charge delivered by said sensor, said capacitor having:further connection terminals connected in parallel with said connectionterminals; and a ferroalectric storage dielectric at leastintermittently connected to said sensor; and a read and reset circuitconnected to said further connection terminals for reading out saidcharge stored in said capacitor.
 2. The circuit according to claim 1,wherein said sensor is a photodiode.
 3. The circuit according to claim1, wherein said sensor is a phototransistor.
 4. The circuit according toclaim 1, wherein said sensor is a Hall sensor.
 5. The circuit accordingto claim 1, wherein said sensor is a thermoelement.
 6. The circuitaccording to claim 1, including a switch connected between one of saidfurther connection terminals of said capacitor and one of saidconnection terminals of said sensor.
 7. The circuit according to claim6, wherein said switch is a transistor and a drive circuit drives saidtransistor.
 8. The circuit according to claim 1, including asemiconductor body, said sensor and said capacitor formed in saidsemiconductor body.
 9. The circuit according to claim 6, wherein: saidferroelectric dielectric saturates at a maximum value; and at least twoof said sensor, said capacitor, and time periods during which saidswitch is on are coordinated with one another to keep an electricalfield present between said further connection terminals of saidcapacitor below said maximum value during a storage procedure.
 10. Thecircuit according to claim 1, wherein: said ferroelectric dielectricsaturates at a maximum value; a switch is connected between one of saidfurther connection terminals of said capacitor and one of saidconnection terminals of said sensor; and at least two of said sensor,said capacitor, and time periods during which said switch is on arecoordinated with one another to keep an electrical field present betweensaid further connection terminals of said capacitor below said maximumvalue during a storage procedure.
 11. The circuit according to claim 6,wherein: said ferroelectric dielectric saturates at a maximum value; andat least two of said sensor, said capacitor and time periods duringwhich said switch is on are coordinated with one another to have anelectrical field present between said further connection terminals ofsaid capacitor reach said maximum value during a storage procedure. 12.The circuit according to claim 11, wherein at least two of said sensor,said capacitor and time periods during which said switch is on arecoordinated with one another to have an electrical field present betweensaid further connection terminals of said capacitor always reach saidmaximum value during a storage procedure.
 13. The circuit according toclaim 10, wherein: said ferroelectric dielectric saturates at a maximumvalue; a switch is connected between one of said further connectionterminals of said capacitor and one of said connection terminals of saidsensor; and at least two of said sensor, said capacitor and time periodsduring which said switch is on are coordinated with one another to havean electrical field present between said further connection terminals ofsaid capacitor reach said maximum value during a storage procedure. 14.The circuit according to claim 13, wherein at least two of said sensor,said capacitor and time periods during which said switch is on arecoordinated with one another to have an electrical field present betweensaid further connection terminals of said capacitor always reach saidmaximum value during a storage procedure.